1. Field of the Invention
The present invention relates to a phase adjusting apparatus, a phase adjusting method for use therein, and a program for such a phase adjusting method, and more particularly to a phase adjusting method for absorbing a differential delay without depending on the pointer stuff in a virtual concatenation of a plurality of VC (Virtual Container)-3 channels of a signal which is made up of multiplexed VC-3 channels.
2. Description of the Related Art
The frame format of an STM (Synchronous Transfer Mode)-16 frame which is made up of multiplexed 48 VC-3 channels is illustrated in FIG. 1 of the accompanying drawings. As shown in FIG. 1, the STM-16 frame comprises section overhead (SOH) 600 for transferring data of a monitoring control system, payload 604, and area 601 for storing pointer information representative of leading ends of multiplexed VC-3 channels.
Payload 604 comprises multiplexed 48 VC-3 channels 602-1 through 602-48. Each of VC-3 channels 602-1 through 602-48 has path overhead (POH) 605 for transferring data of the monitoring control system.
For handling a plurality of VC-3 channels 602-1 through 602-48 as a single data transfer area, virtual concatenation has been standardized by G.707/G783 of ITU-T (International Telecommunication Union-Telecommunication Standardization Sector).
For example, it is assumed that three VC-3 channels are handled as a virtual concatenation and will be transferred from node 71 to node 76 as shown in FIG. 2 of the accompanying drawings. Since each of the VC-3 channels may possibly be transferred through one of three paths 701, 702, 703, the VC-3 channels that are received by node 76 are brought out of phase with each other due to device delays caused by intermediate nodes 72-75 and delays caused by different path lengths. Therefore, some scheme is necessary to absorb the phase differences at the node which terminates the virtual concatenation.
According to the virtual concatenation, H4 byte 603 of path overhead 605 of each VC-3 channel stores MFI (Multi-Frame Indicator) which is a number representative of the order of the VC-3 channels as a scheme for detecting and processing the phase differences.
FIG. 3 of the accompanying drawings shows MFI values stored at H4 bytes. The concept of pointer stuff of SDH/SONET (Synchronous Digital Hierarchy/Synchronous Optical NETwork) will be described below with reference to FIGS. 1 through 3.
If nodes 71, 76 shown in FIG. 2 operate according to independent clocks, i.e., nodes 71, 76 have respective clock sources, nodes 71, 76 have slightly different clock speeds due to different accuracies of their clock sources.
The STM-16 frame has stuff areas 606, 607 for transferring the data normally regardless of the different clock speeds of nodes 71, 76. If the clock speed of the transmission node is higher than the clock speed of the reception node, then stuff area 606 in SOH 600 is used as a data area thereby to increase the number of bytes that can be transferred per frame, so that the data can be received at the clock speed of the reception node. If the clock speed of the transmission node is lower than the clock speed of the reception node, then stuff area 607 in payload 604 is not used as a data area thereby to reduce the number of bytes that can be transferred per frame.
When the transmission and reception nodes operate according to independent clocks, if a differential delay of a virtual concatenation is absorbed by a memory, then the buffer suffers an underflow or an overflow at the time the stored data is read at a constant rate. The buffer may be prevented from suffering an overflow when the stored data is read at a rate higher than when the data is written. However, when the buffer suffers an underflow, it is necessary to recognize the timing at which the data is to be read again.
For example, if a virtual concatenation comprises VC-3#1 channel, VC-3#2 channel, and VC-3#3 channel, then since the data is mapped one byte by one byte in the order of VC-3#1 channel, VC-3#2 channel, and VC-3#3 channel at a data mapping node, the data needs to be read one byte by one byte from VC-3#1 channel, VC-3#2 channel, and VC-3#3 channel at a data restoring node.
Consequently, when an underflow occurs, it is necessary to start reading the data at such a timing that at least one byte of data needs to be stored in the memory for storing the VC-3 channels of the virtual concatenation. Stated otherwise, the reading node is required to recognize, at all times, whether data is stored in the memory or not. One process of determining whether data is stored in the memory or not is to manage and compare write and read addresses of storage areas which are reserved in a phase adjustment memory for storing the VC-3 channels.
However, the above conventional phase adjusting process is problematic in that the circuit required for performing the process is complex and large in scale because it is necessary to determine, at all times, whether data of each of the VC-3 channels is stored in the phase adjustment memory or not based on the write and read addresses, and when data of all the VC-3 channels of the virtual concatenation are stored, the stored data need to be read.
The phase adjustment memory usually comprises an external memory, and storage areas thereof for storing respective VC-3 channels are managed with write and read addresses. Therefore, as the number of multiplexed VC-3/VC-4 channels and storage areas (addresses) are larger, the required circuit is more complex and larger in scale.